- GATE 2018
A pipelined processor with separate instructions and data cache has 5 stages , the cycle time is 30 ns.It can start a new instruction on every cycle when there are no hazads.It is used with copy back data cache with a block size of one word.
Tcache = 30ns , TMainmem = 80ns.
The hit ratio of the cache is 90%.Ignore write back times of dirty pages.If 35% of the instructions are Load and Store which only results in hazards.
1.What is the throughput of the CPU???
How many stall cycles occur when a memory access instruction misses in the cache??