A pipelined processor with separate instructions and data ca

A pipelined processor with separate instructions and data cache has 5 stages , the cycle time is 30 ns.It can start a new instruction on every cycle when there are no hazads.It is used with copy back data cache with a block size of one word.

Tcache = 30ns , TMainmem = 80ns.

The hit ratio of the cache is 90%.Ignore write back times of dirty pages.If 35% of the instructions are Load and Store which only results in hazards.

1.What is the throughput of the CPU???

How many stall cycles occur when a memory access instruction misses in the cache??

1Comment
Arvind Rawat arvind.rawat 9 Dec 2014 02:18 pm

Average memory access time = 0.9 * 30 + 0.1 * (30+80) = 38ns
Minimum clock cycles required for a memory access = ceil(38/30) = 2
Now, 35% instructions(hazards) are load and store, which required 2 cycles and rest of the 65% require only 1 cycle;
On average no. of cycles required to execute one instruction = 0.35 * 2 + 0.65 * 1 = 1.35

Now, the memory cycle time is given as 30ns, therefore, no of memory cycles in 1 sec = 1 / (30*10-9) = 33.33 * 106
So, CPU speed = 33.33 * 106 / 1.35 = 24MIPS.