Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, We can say that

(A) T1<=T2

(B) T1>=T2

(C) T1<T2

(D) T1 = 2T2



sumitverma's picture

In pipelining the entire circuit is devided into various units. So in between these units some delay will occur.

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