Consider a machine with 10 ns clock and it takes 4 clock cycle per ALU instruction, 5 clock cycle per branch instruction, 6 clock cycle memory instruction. There exists 40% ALU instruction, 20% branch instruction, and 40% memory instruction. What is the speed up factor achieved by above system if overhead is 2 ns?

(A) 3.17

(B) 4.17

(C) 5.17

(D) 6.17

Hint: 

Responses

sumitverma's picture

Average access time for non pipeline system
(4 × 0.40 + 5 × 0.20 + 0.40 × 6) × 10 ns + (1.6 + 1 + 2.4) × 10 ns = 50 ns
For pipeline system, in every clock cycle, one instruction will get executed and overhead of 2 ns.
So, average time = (10 + 2) ns = 12 ns
Speed up factor = 50/12 = 4.17

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