An instruction pipeline has five stages where each stage takes 2 nano seconds and all instructions use all 5 stages. Branch instructions are not overlapped, i.e., the instruction after the branch is not fetched till the branch instruction is completed under ideal conditions. If a branch instruction is a conditional branch instruction, the branch need not be taken. If the branch is not taken, the following instructions can be overlapped when 80% of all branch instructions are conditional branch instruction, and 50% of the branch instructions are such that the branch is taken. What is the average instruction execution time?

(A) 4 milli seconds

(B) 3.6 milli seconds

(C) 2.96 nano seconds

(D) 3.74 nano seconds



More Comments
habibkhan's picture

But for conditional branch according to the question the branch should be taken only if the condition evaluates to be true which is happening 50% of the time..

So none of the options are matching with this approach..

sumitverma's picture

20% are branch
80% of branch are conditional ,implies 80% of 20% are conditional
which means 20% are unconditional(always takes), implies 20% of 20% are unconditional which are taken 50% of branch conditional are taken, implies 50% of 80% of 20% are taken considering for all cases where there is stall : therefore,

Tavg=(1+stall cyle*stall freq) clocks
 = (1+ ( 0.50*0.80*0.20*4 ) + (0.20*0.20*4) ) clocks
 = 1.48 clocks= 1.48 * max{stage dealy}= 1.48*2ns= 2.96 ns

where it is given 20% instructions  are branch instructions???

hradeshpatel's picture

yes none of the option match

@sumitverma, statemet is like

80% of all branch instructions are conditional branch instruction

its not given that 20% are branch

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