A 4-stage pipeline has the stage delay as 150, 120, 160 and 140 nano seconds respectively. Registers that are used between the stages have a delay of 5 nano seconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be ________________ μ sec (correct to 1 decimal place).


sumitverma's picture

Tn = (K + n − 1)Tclock pipeline

hradeshpatel's picture

i save the answer 165.4 . so its wrong........

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