Consider the unpipelined machine with 10 nano seconds clock cycles. It uses four cycles for ALU operations and branch where as 5 cycles for memory operation. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the machine adds 1 nano second overhead to the clock. _____________ times speed up in the instruction execution rate is gained from a pipeline.

Responses

sumitverma's picture

(1 + branch frequency * penalty + ALU frequency * penalty + memory frequency * penalty) * clock period

ashokwa's picture

how please explain properly 

 

shikhar's picture

Time(without pipelining)=(.4x4+.2x4+.4x5)x10=44

Time(with pipelining)=10+1=11

SpeedUp=44/11=4

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