Short notes on Instruction pipelining


Here is short notes on one of the most important topics of COA i.e. instruction pipelining :

There are a few considerations required as far as the pipelining problems solving is concerned ..These conclusions I have drawn on the basis of previous years questions that have come on this topic :

a) Speedup is a general terminology and hence used in any of the designs , be it memory , I/O or for that matter CPU..For memory we can define speedup in terms of access time of main memory and cache memory..Similarly in case of I/O , we can define speedup in terms of I/O time taken in programmed I/O mode and that in interrupt handling mode..


b) Finding hazards ( RAW , WAR , WAW )  pipeline is more difficult than finding dependencies..As for dependencies we can apply Bernstein's conditions and arrive at the dependencies in the instruction set..But to consider hazard , we have to consider the instructions in the pipeline whether or not the stalls are being created or not due to that particular dependency or not..In that case only ,  dependency becomes a hazard else not..

c) There is a common misconception prevalent that true dependency is defined for consecutive instructions only which is not the case..That is why it is safe to use the Bernstein's conditions..

d) For solving problems based on execution completion time of instruction set in a pipeline , everything is mentioned in the question clearly i.e. whether operand forwarding to be used or not etc..By default in Hamacher , it is mentioned that if we have no opernad forwarding then register read and register write operations in the WB stage of pipeline are in separate clock cycles ..Thus after WB completion one more stall is incurred then only we go to compute(execute) stage of pipeline..However if  register write followed by register read occurs in the same cycle of WB stage then execute stage can be performed just after the WB stage of the previous instruction concerned of which the current instruction is using the data..Also Load / Store instructions find special place as even though the operand forwarding is enabled they will incur a stall ; the reason being that

load / store output is given by interface register till MA stage so we have to wait till then..

Thus operand forwarding minimises but does not elimintate stalls completely..


e) Similar consideration required for branch instruction..It will be mentioned in the question which method is used to deal with branch (or control hazards) ..It can be delayed branching or branch prediction technique..


Hope this helps..:)