DMA (Direct Memory Access)

What is DMA and why we need it?

The problem with both interrupt driven and programmed I/O is the "involvement of processor or CPU" when we have to perform I/O operation between main memory and I/O devices.

Thus, both these forms of I/O suffer from two inherent drawbacks:
1. The I/O transfer rate is limited by the speed with which the processor can test
and service a device.
2. The processor is tied up in managing an I/O transfer; a number of instructions
must be executed for each I/O transfer.

When large volumes of data are to be moved, a more efficient technique is required: direct memory access (DMA).


DMA involves an additional module in system bus and it is capable of taking the control of system buses from the processor. For this purpose, the DMA module must use the buses when the processor is not using them or it can ask for access to control buses from the processor.


The DMA module transfers the entire block of data, one word at a time, directly to or from memory, without going through the processor.
When the transfer is complete, the DMA module sends an interrupt signal to the
processor. Thus, the processor is involved only at the beginning and end of the transfer

Let's talk about pins:-

Pins in CPU: or processor-

Interrupt pin:- It is going to tell CPU whether an interrupt has been raised or not.

BR: When a request signal comes from DMA saying that I need to use the bus.

BG: It is said to be set when the CPU accepts the DMA request and told DMA to use the bus.

BG=0 means Bus is not granted to DMA

BG=1 means Bus is granted to DMA.

Common pins:-

RD: When you have to read something from memory , put this pin-up.

WR: when you have to write something from Memory to I/O device.


DMA works in two modes:

1. Burst Mode

2. Cycle stealing mode.

1. Burst mode:

While dealing with high-speed devices like hard disk once DMA got access to bus, it is not going to leave the bus until all operations are completely performed.


2. Cycle stealing mode.

  1. Used to deal with slower devices.
  2. Transparent way of taking the bus when the CPU is using them.
  3. When DMA forces the processor to suspend operation temporarily. This is called cycle stealing mode.


Daisy Chaining

Daisy Chaining:-

  1. It implements a vector interrupt.
  2. It provides non-uniform priority to interrupting devices. It means the device with the highest priority is connected in the first place.
  3. There is a single processor data bus.


The interrupt acknowledges line is daisy chained through the modules. When the processor senses an interrupt, it sends out an interrupt acknowledge. This signal propagates through a series of I/O modules until it gets to a requesting module. The device that is connected in the first place will see the interrupt acknowledge before anyone. If the interrupt is really sent by this, it will forward 0 and if not then it will do nothing on seeing the acknowledgment bit.




Hardware Based Interrupt and Vectored Interrupt(1)

Before going into details let's know some basic things.

1. Vectored Interrupt:-

    In Physics, vector means both magnitude and direction.

The device which is causing the interrupt provide the starting address of ISR (interrupt service routine.)

2.Non- vectored Interrupt: - The Interrupting device is not going to provide starting address of ISR. You have to go and ask for each device individually.


Hardware-Based Interrupt:

A hardware interrupt has few properties:

  1. It is vector Interrupt.
  2. No polling.
  3. It is faster as compared to software interrupt.

The hardware-based interrupt can be implemented in two ways:

1. Daisy Chaining.

2. Parallel chaining.

let's see both of them.


Ambikesh Kumar Singh @ambikeshkumarsingh
1 Jul 2019 11:27 am
It's up now.
Interrupt-Driven I/O

The problem with programmed I/O is that the processor has to wait a long time for the I/O module of concern to be ready for either reception or transmission of data. The processor, while waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of the performance of the entire system is severely degraded.

How Interrupt-Driven I/O works??

  1. Let's say our processor needs some I/O data then it will send a read command to I/O module after this processor will go to do some different work.
  2. At the end of each instruction cycle, the processor checks for interrupts.
  3. The I/O module will act as an associate and it will go to read in the data.
  4. Once the data is present in its register, it is going to send an interrupt signal to the processor through the command line.
  5. When the interrupt from the I/O module occurs, the processor saves the context (e.g., program counter and processor registers) of the current program and processes the interrupt.
  6. In this case, the processor reads the word of data from the I/O module and stores it in memory. It then restores the context of the program it was working on (or some other program) and resumes execution.


                                   This figure shows simple interrupt processing.

Interrupt I/O is more efficient than programmed I/O because it eliminates needless waiting. However, interrupt I/O still consumes a lot of processor time, because every word of data that goes from memory to I/O module or from I/O module to memory must pass through the processor.


Now we will discuss design issues arise in implementing interrupt I/O.

Programmed I/O

With programmed I/O, data are exchanged between the processor and the I/O module. The processor executes a program that gives it direct control of the I/O operation, including sensing device status, sending a read or write command, and transferring the data. When the processor issues a command to the I/O module, it must wait until the I/O operation is complete.


Step 1: Read the Status flag.

Step 2: If data is not available ie, 

      ( status =0) then go to step 1.

Step 3: take the I/O data.


This is a busy waiting solution if data is not available the processor has to keep doing step 1.

If the processor is faster than the I/O module, this is wasteful of processor time.

Typically, there will be many I/O devices connected through I/O modules to
the system. Each device is given a unique identifier or address. When the processor issues an I/O command, the command contains the address of the desired device.
Thus, each I/O module must interpret the address lines to determine if the command is for itself.

When the processor, main memory, and I/O share a common bus, two modes
of addressing are possible: memory mapped and isolated

Now we will discuss what is memory mapped and Isolated.