Pipelining Hazards

Pipeline Hazards:-

A pipeline hazard occurs when the pipeline, or some portion of the pipeline,
must stall because conditions do not permit continued execution. Such a pipeline stall is also referred to as a pipeline bubble.


There are three types of hazards:
 resource, data, and control.

​This Hazard is just because of Resource restriction. example:-

Story: Let us say two friends urgently needed to use the toilet at the same time but only one toilet is available. The condition is that they can't wait till other finishes.

So what is the appropriate solution :

Build a replica of the toilet so that they both can use whenever they want. 


A resource hazard occurs when two (or more) instructions that are already in the pipeline need the same resource. The result is that the instructions must be executed in serial rather than parallel for a portion of the pipeline. A resource hazard is sometimes referred to as a structural hazard.


Resource duplication is the only way to handle this hazard. We need to create multiple copies of shared resource so that different instruction can use different copies of resources simultaneously.



A data hazard occurs when there is a conflict in the access of an operand location.


Understand this hazard as :

Your girlfriend is staying with you and she is cooking food for you and she told you that the cooking process will be finished at 11 pm but you want the food at 10 pm. This will lead to a HAZARD. Here food is our data which is needed by both of you but at different time. We will shortly discuss what happens next.


In general terms, we can state the hazard in this form:- Two instructions in a program are to be executed in sequence and both access a particular memory or register operand. If the two instructions are executed in strict sequence, no problem occurs.

However, if the instructions are executed in a pipeline, then it is possible for the operand value to be updated in such a way as to produce a different result than would occur with a strict sequential execution. In other words, the program produces an incorrect result because of the use of pipelining.



The first instruction adds the contents of the 32-bit registers EAX and EBX
and stores the result in EAX. The second instruction subtracts the contents of EAX from ECX and stores the result in ECX.


The figure shows pipeline behavior.
The ADD instruction does not update register EAX until the end of stage 5, which
occurs at clock cycle 5. But the SUB instruction needs that value at the beginning of its stage 2, which occurs at clock cycle 4.To maintain correct operation, the pipeline must stall for two clocks cycles


There are three types of data hazards:-

Informal talk: let assume read means "eat" and Write means " cook".


 1.  Read after write (RAW) or true dependency: -An instruction modifies a register or memory location and a succeeding instruction reads the data in that
memory or register location. A hazard occurs if the read takes place before the
write operation is complete. 

Story:-Your girlfriend has already told you that you can eat after 11 pm but you want it at 10 pm because you have some different plans. If you eat food before 11 pm, let's say at 10:30 pm either the food will be half cooked or tasteless and most importantly she will be hyped. So the only solution is to keep patience and to eat after 11 pm.

Now in a formal language, let her finish her writing and then you read.


• Write after Read (WAR), or anti-dependency: An instruction reads a register or memory location and a succeeding instruction write to the location.

A hazard occurs if the write operation completes before the read operation takes place.

Story:- Now, You want to cook something for her but she is still eating and you are asking repeatedly that what will she eat next. she will be very annoyed. So the best way to deal with this situation is to let her finish eating first then you talk about cooking.

Write after write (RAW), or output dependency: Two instructions both write
to the same location. A hazard occurs if the write operations take place in the
reverse order of the intended sequence.


I1: R1 <-- R2 + R3

I2:  R1 <-  R4 + R5

here both I1 and I2 are trying to write on I1.



A control hazard, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

Until the instruction is actually executed, it is impossible to determine whether the branch will be taken or not.

Various techniques to deal with conditional branches:-

  • Multiple streams
  • Prefetch branch target
  • Loop buffer
  • Branch prediction
  • Delayed branch