Carry Look Ahead Adder

In order to overcome the disadvantaged of Ripple carry Adder, we use carry look ahead Adder. 

The problem with ripple carry adder is a dependency on the previous stage for carry bit.



Note:   C_{n} will be 1 if: C_{n-1} is 1 and either of two input is 1 or Both inputs are 1

               In other words, we can write is as 

               C_{n}= C_{n-1}(A_{n-1} \oplus B_{n-1}) + A_{n-1}B_{n-1}

               The reason we are using \oplusis: It gives output 1 when either of one input is 1


Step 1: Writing carry equation

C_{1}= C_{0}(A_{0} \oplus B_{0}) + A_{0}B_{0}

C_{2}= C_{1}(A_{1} \oplus B_{1}) + A_{1}B_{1}

C_{3}= C_{2}(A_{2} \oplus B_{2}) + A_{2}B_{2}

C_{4}= C_{3}(A_{3} \oplus B_{3}) + A_{3}B_{3}

let's assume 

G_{i}= A_{i}B_{i}              //  generating term

P_{i}= A_{i}\oplus B_{i}      //    propagation term


Step 2: rewriting the carry equation in terms of P_{i} and G_{i}

C_{1}= C_{0}(P_{0})+ G_{0}

C_{2}= C_{1}(P_{1})+ G_{1}

C_{3}= C_{2}(P_{2})+ G_{2}

C_{4}= C_{3}(P_{3})+ G_{3}


Step 3: removing carry dependency   

C_{1}= C_{0}(P_{0})+ G_{0}

C_{2}= (C_{0}(P_{0})+ G_{0})P_{1} + G_{1}

C_{3}= ((C_{0}(P_{0})+ G_{0})P_{1} + G_{1})P_{2} + G_{3}

C_{4}= (((C_{0}(P_{0})+ G_{0})P_{1} + G_{1})P_{2} + G_{3})P_{3} + G_{3}

C_{4}= C_{0}P_{0}P_{1}P_{2}P_{3} + G_{0}P_{1}P_{2}P_{3}+ G_{1}P_{2}P_{3}+G_{2}P_{3} + G_{3}

Now, we can clearly see that there is no carry dependency except C_{0}

Final Picture:



Total number of AND gate used is: 10

Total number of OR gate used is: 4


Contributor's Info

Ripple Carry Adder

Ripple Carry Adder:-

  1. A ripple carries adder is an arithmetic circuit that produces a sum of two binary numbers.
  2. It can be constructed using full adders connected in cascading order.
  3. In ripple carry adder output is known after the carry generated by the previous stage is produced.
  4. the sum of the most significant bit is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage. As a result, the final sum and carry bits will be valid after a considerable delay.

to let us say we have two- 4 digit binary number :

A and  B and their bits configuration are like:

A =a_{3}a_{2}a_{1}a_{0}

B =b_{3}b_{2}b_{1}b_{0}

 c_{0} is initial carry then 


This can be implemented using 4 full adders like this.


Problem with ripple carry adder:

  1. To start any stage you need to carry from the immediately previous stage.
  2. All full adders are not working parallelly, they need carry to work.
  3. If there are n bits the total delay = n *  full adder delay


Contributor's Info

Combinational Circuits

Combinational Circuits

 A combinational circuit is consist of input variables,logic gates and output variables.The logic gates accept signal from input and generate signal to the outputs.The block diagram of combinational circuits can be drawn as :

Both input and output data are represented by binary signals therefore for N input variables there are total  2possible combinations of binary input values.  


Contributor's Info