D Flip-Flop

D FLIP-FLOP

BLOCK DIAGRAM:

 

  • When the clock (Clk) input is LOW “0” then there is no change from the output. It does not respond when the clock input is LOW. When we apply the clock HIGH “1” then it works normally and output varies as shown below tables.

 

TRUTH TABLE:

Clk

D

Qn+1

0

X

Qn

1

0

0

1

1

1

 

  • For the D Flip-Flop what we give input that is only the output

CHARACTERISTIC TABLE:

D

Q

Qn+1

0

0

0

0

1

0

1

0

1

1

1

1

 

  • D Flip-Flop (Delay flip-flop) is connected to SR with one is connected to D input and another one is connected to the inverter of the D input.

 

CHARACTERISTICS EQUATION:

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