Gate 2005
Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

A.3
B.4
C.5
D.6

3Comments
Sumit Verma @sumitverma
31 Jan 2017 04:06 pm
Ruchika @ruchikalakhi
31 Jan 2017 09:27 pm

But what about memory reference cycles for instruction decode phase?

MD IMRAN HUSSAIN @mdimranhussain76
26 Aug 2017 05:43 am

According to me answer should be 6 .

bcoz

IF-1MR

ID-2MR

OF-3MR

PD-   -there is no ALU operation

WB-1MR

Hence memory cycles neede during execution cycle of the instruction=ID+OF+PD+WB

                                                                                                                 =2+3+0+1

                                                                                                                  =6   Ans

 

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