MultiLevel Caches

How to solve these kind of question

3Comments
Arul @innovwelt
5 Feb 2015 01:21 am

check with the answer given

L1 hit ratio = 450/500 = 0.9

L2 hit ratio = 30/50 = 0.6

Average memory access = 0.9*(10) + 0.1*(0.6*(10+20) + 0.4*(10+20+100))

= 16 cycles

Average stall cycles per instruction = 2.5*16 = 40 cycles

Lakshmi Bansal @lakshmibansal
5 Feb 2015 05:24 pm

the answer given is 15
 

Kunal Chalotra @kunalchalotr
18 Jul 2015 10:59 pm

in 500 memory reference there are total 200 instruction ..because they are given in question 2.5 memory reference per instruction...

avg memory stalls=(misses_in _L1/ total instruction* hit _time+ misses_in_L2* MIss_PENALITY)

=50/200 *20+20/200 *100

=2.5*20+10

=5+10

=15 ans

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