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multilevel paging
A processor uses 36 bit physical address and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

Bits 30-31 are used to index into the first level page table.
Bits 21-29 are used to index into the 2nd level page table.
Bits 12-20 are used to index into the 3rd level page table.
Bits 0-11 are used as offset within the page.

The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively

a) 20,20,20
b) 24,24,24
c) 24,24,20
d) 25,25,24

Arvind Rawat @arvind.rawat
4 Dec 2015 11:06 am