Anonymous user menu

A processor uses 2-level page tables for virtual to physical

A processor uses 2-level page tables for virtual to physical address translation. Page

tables for both levels are stored in the main memory. Virtual and physical addresses are

both 32 bits wide. The memory is byte addressable. For virtual to physical address

translation, the 10 most significant bits of the virtual address are used as index into the

first level page table while the next 10 bits are used as index into the second level page

table. The 12 least significant bits of the virtual address are used as offset within the

page. Assume that the page table entries in both levels of page tables are 4 bytes wide.

Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%.

The TLB caches recently used virtual page numbers and the corresponding physical page

numbers. The processor also has a physically addressed cache with a hit rate of 90%.

Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is

also 1 ns.



78. Assuming that no page faults occur, the average time taken to access a virtual

address is approximately (to the nearest 0.5 ns)

(A) 1.5 ns (B) 2 ns (C) 3 ns (D) 4 ns



79. Suppose a process has only the following pages in its virtual address space: two

contiguous code pages starting at virtual address 0×00000000, two contiguous

data pages starting at virtual address 0×00400000, and a stack page starting at

virtual address 0×FFFFF000. The amount of memory required for storing the page

tables of this process is

(A) 8 KB (B) 12 KB (C) 16 KB (D) 20 KB

 

can anyone give me solution to second part i.e. 79 question please???

I dont know how to solve it

1Comment
Arvind Rawat @arvind.rawat
8 Dec 2014 09:05 pm

First level page table is addressed using 10 bits and hence contains 210 entries. Each entry is 4 bytes and hence this table requires 4 KB. Now, the process uses only 3 unique entries from this 1024 possible entries (two code pages starting from 0x00000000 and two data pages starting from 0x00400000 have same first 10 bits). Hence, there are only 3 second level page tables. Each of these second level page tables are also addressed using 10 bits and hence of size 4 KB. So, total page size of the process = 4 KB + 3*4 KB = 16 KB