##### TLB and Pagefault

#Gate2004

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

(A) 645 nanoseconds

(B) 1050 nanoseconds

(C) 1215 nanoseconds

(D) 1230 nanoseconds

plz solve it in detail

Pritam Prasun
13 Jan 2016 09:32 pm

Avg time To Execute Instruction = CPU Time + Memory Access Time

Give that CPU Time = 100 ns
for an instruction probability of having page fault = 1/10000
Hence, probability of having not a page fault = 9999/10000

If TLB hit occurs then memory Access time = 150 +150 = 300 and
if TLB miss occurs then Memory Access Time = Access Page Table1 + Page table2 + Two memory Access =150 + 150 + 150 + 150 = 600

Hit ratio of TLB = 90 %

Memory Access Time = 9999/10000 ( 0.90*300 + 0.10*600 ) + 1/10000( 8000000 + .90*300 + .10*600 )
= 329.967 + 800.033
= 1130 ns

Total Time of execution is = CPU Time + Memory Access Time
Total Time of execution is = 100 ns + 1130 ns = 1230ns

Anmolpreet Kaur
14 Jan 2016 01:03 am

WHY TLB hit contains two memory accesses?

Digvijay Pandey
24 Jan 2016 03:07 pm

Two access because of two Level Memory

20 Jan 2017 04:33 pm

why 8000000??

Jagmeet
21 Jan 2017 11:22 am

@sharddhagami   because 8 ms ⇒ 8*10^6 ns.

Satya Prakash @sprp
14 Jan 2016 09:22 pm

-

11 Jan 2017 10:38 pm

Average Instruction execution time

= Average CPU execution time + Average time for getting data(instruction operands from memory for each instruction)

=   Average CPU execution time
+ Average address translation time for each instruction
+ Average memory fetch time for each instruction
+ Average page fault time for each instruction

= 100+2(0.9(0)+0.1(2×150))+2×150+(1/10000)×8×10^6

(Page Fault Rate per 10,000 instruction is directly given in question.Two memory accesses per instruction and  hence we need 2 ×address translation time for average instruction execution time)

[ TLB access time assumed as 0 and 2 page tables need to be accessed in case of TLB miss as the   system uses two-level paging ]

= 100+60+300+800

= 1260ns

Pankaj Naik
23 Jul 2019 06:31 pm
@jagmt, 8ms is 8x10^(-3)sec.