Virtual GATE 2015 - Question 38

Given Answer: 221
Discuss the solution.

6Comments
Arul @innovwelt 29 Jan 2015 11:56 am

totally 6 instructions are executed. I1, I2, I3, I4, I9, I10 = (6+5-1) (12+5) = 170

During I4, only after the Execute Instrution(EI) stage, I9 is feteched. So, 3 cycles are wasted. 3 * 17 = 51

170 + 51 = 221.

Mv Prasad @mvprasad 29 Jan 2015 01:46 pm
Total it take 13 cycles.
Cycle time is 12+5=17.
13*17=221.
Mv Prasad @mvprasad 29 Jan 2015 01:47 pm
Total it take 13 cycles.
Cycle time is 12+5=17.
13*17=221.
vishal @vishal92 29 Jan 2015 01:01 pm

innowelt why after execution stage ,target address is available in 2nd stage so only 1 cycle waste
how u know that target address is avail after 3rd stage

 

Arul @innovwelt 29 Jan 2015 02:06 pm

I quote from wikipedia: http://en.wikipedia.org/wiki/Branch_predictor

"Without branch prediction, the processor would have to wait until the conditional jump instruction has passed the execute stage before the next instruction can enter the fetch stage in the pipeline."

Vivek Vikram Singh @vivek14 29 Jan 2015 05:31 pm

Upon drawing the pipeline diagram,Because of I4, I8 is the only instruction which does not to enter in Pipeline ,hence not executed.
So total number of instructions which got executed is  : 9.
Cycle time =  Max ( delays ) + Register delay
 = 12 + 5 = 17ns
 
 SO total time for this = (k+n-1 )* cycle time, k = number of stage , n = number of instructions.
 = (5+9-1) * 17 = 13 * 17 = 221 ns

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