Consider a non-pipelined processor with a clock rate of 2.5 giga-hertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 giga-hertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.
ANSWER : (3.2)
Non-Pipelined processor : For n instructions execution time =(n*4) / 2.5 = 1.6n nanoseconds
Pipelined processor : For n instructions execution time =n / 2 = 0.5n nanoseconds
Speed-Up : = 1.6n / 0.5n =3.2