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Page Table Entry

A control bit, C, in each page table entry determines if memory references to that page are cacheable. In order to support this feature, which of the following statements concerning the interaction between virtual-to-physical address translations and caching must be true?

(A) Easy memory access requires a virtual address translation to take place in parallel with the cache access.
(B) The status of the cacheable bit, C, needs only to be considered on a cache miss
(C) Page table entries with their dirty bit set should clear their cacheable bit
(D) All of the above