An unpipelined machine with 10 ns clock cycles. Its ALU operations use four cycles and branches whereas five cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20%, 40% respectively. Let due to clock skew and setup pipelining, the machine adds 1 ns of overhead to the clock. The speed in the instruction execution rate will gain from a pipeline will be _____________ times (integer value only).
Average instruction execution time = clock cycle × average CPI
= 10 ns × [(40% + 20%) × 4 + 40% ×5]
= 10 ns × 4.4
= 44 ns
In pipeline clock must run at speed of slowest stage to overhead
Average instruction execution time = 10 + 1 = 11 ms
Speed up = Average instruction time unpipelined / Average instruction time pipelined = 44 ns / 11 ns = 4 times.