A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.
A. 4 time units
B. 6 time units
C.10 time units
D.12 time units

##### 1Comment
Rohit Panwar
18 Nov 2019 06:39 pm
@manish
The 4-bit addition will be calculated in 3 stages:
1) (2 time units) In 2 time units we can compute Gi and Pi in parallel, 2 time units for Pi since its an XOR operation and 1 time unit for Gi sinceits an AND operation.
2) (2 time units) Once Gi and Pi are available, we can calculate the carries, Ci, in 2 time units.
Level-1 we can compute all the conjunctions (AND). Example P3G2, P3P2G1, P3P2P1G0 and P3P2P1P0C0 which are required for C4.
Level-2 we get the carries by computing the disjunction (OR).
3) (2 time units) Finally, we compute the sum in 2 time units, as its a XOR operation.
Hence, the total is 2+2+2=6 time units.