Gate2001_2.8

Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C \(\ge\) 40 nanosecond. Which one is the correct plot of Y?

 

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